Few things that took me a while to figure out:
1. When using high and low priority interrupts, GIEH must ALSO be enabled along with GIEL (bits 7 and 6) for low priority interrupts to occur.
2. Even when interrupts are not enabled (such as external interrupts on INT0), these are still being flagged. Thus, if there are multiple sources of interrupts and if the interrupt source checking is not handled carefully, disabled interrupt routines may still occur. For example, in my…
ContinueAdded by Soon Kyu Lee on February 22, 2013 at 2:18am — No Comments
Code given in textbook is something like this:
WR_INS
bcf RS ;clear Register Status bit
movwf temp_lcd ;store instruction
andlw 0xF0 ;mask 4 MSB
movwf LATD ;send 4 MSB
bsf E ;pulse enable high
call delay5ms
swapf temp_lcd, 0 ;swap nibbles (result into WREG)
andlw 0xF0 ;mask 4 LSB
bcf E
movwf LATD ;send 4 LSB
bsf E ;pulse enable high
nop
bcf E
call delay5ms ;allow time for change
return
But this does not…
ContinueAdded by Soon Kyu Lee on February 3, 2013 at 5:00pm — No Comments
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