Instruction decoder verilog

In Verilog code create an instruction decoder. Instructions supported by the ISA can have instructions that are up to two words in length. Due to this, the decoder will be able to account for the variable length. Develop the basic idea of how the datapath will be laid out. Include a preliminary diagram of the datapath. Provide a working testbench. Objective: To implement and test the Instruction Decode (ID) pipeline stage and integrate it with the IF stage. This is part of a series of labs to implement the MIPS Datapath (figure1.1on pageLab 1-2) as a behavioral model in Verilog and simulate it. Write verilog code for the instruction decoder with the interface shown in Figure 2 of the lab manual. Verify your code using Vivado simulator and make sure there is no syntax error in the code. Search for jobs related to Instruction decoder verilog or hire on the world's largest freelancing marketplace with 19m+ jobs. It's free to sign up and bid on jobs. Question: Write Verilog code to create an instruction decoder. Remember that the instructions supported by our ISA can have instructions that are up to two words in length. For this reason, the decoder must be able to account for the variable length. You must develop at least a basic idea of how your datapath will be laid out. Please include a Search for jobs related to Verilog code instruction decoder or hire on the world's largest freelancing marketplace with 20m+ jobs. It's free to sign up and bid on jobs. Decoder. Feb-9-2014 : Decoder - Using case Statement : 1 //----- 2 // Design Name : decoder_using_case 3 // File Name : decoder_using_case.sv 4 // Function : decoder using case 5 // Coder : Deepak Kumar Tala 6 //----- 7 module decoder_using_case ( 8 input wire [3:0] binary_in , // 4 bit binary input 9 output reg [15:0] decoder_out , // 16-bit out 10 input wire enable // Enable for the decoder